Realization of Automatic Test Pattern Generator Enabled Uart Using Verilog

Testing of VLSI chips is changing into significantly complicated day by day as a result of increasing exponential advancement of NANO technology. BIST may be a style technique that enables a system to check mechanically itself with slightly larger system size. During this paper, the simulation result performance achieved by BIST enabled UART design through VHDL programming is enough to compensate the additional hardware required in BIST design. this system generate random check pattern exploitation the LFSR checks Pattern Generator mechanically, therefore it will offer less check time compared to associate degree outwardly applied check pattern and helps to attain rather more productivity at the top modules. This mechanism also to be used to check the design chip itself. So the main advantage of this testing is that it reduces the complexness thereby will increase the operational speed, potency in conjunction with relevant price reduction. Also in this method the conjunction with operation, maintenance of the system may also be done.